Difference between revisions of "Broadway"

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The '''Broadway''' is the Wii's main CPU. It is a 32-bit PowerPC CPU based on the PowerPC 750CL. It is based on the GameCube [[Gekko]] CPU design, being almost identical other than an overclock and the addition of the HID4 register.
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The '''Broadway''' is the Wii's main CPU. It is a 32-bit PowerPC CPU based on the PowerPC 750CL. It is based on the GameCube [[Gekko]] CPU design, being almost identical other than an overclock and the addition of a few new features.
  
== Versions ==
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== New features from Gekko ==
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(following text copied from official document "Summary of changes to Gekko User's Manual to turn it into a Broadway User's Manual")
  
* DD1.0
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The major changes from Gekko to Broadway, covered in the UM are:
* DD1.01
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* DD1.2
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* 1) L2 cache configurable for 32-B fetch mode, 64B-fetch mode or 128B-fetch mode
* DD1.3
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* 2) Deeper pipelining on the 60x bus, programmable to max depth of 2, 3 or 4
* DD2.0 (final)
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* 3) Number of BATs is increased from 4 to 8 each for I and D
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* 4) Addition of the HID4 register (SPRN = 1011) to control the new features.
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* 5) TAU functionality is eliminated (but the THRM1-3 regs remain)
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* 6) PLL configuration (processor-to-bus frequency ratio) expanded
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* 7) Several changes to the signal pins - DRTRY, TLBISYNC, PLL_CFG[4]
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* 8) Several Gekko errata are fixed on Broadway.
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* 9) The PVR is initially 0x00087100 on Broadway.
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==Versions==
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 +
*DD1.0
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*DD1.01
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*DD1.2
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*DD1.3
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*DD2.0 (final)
  
 
Source: clkspeed.dol in [[RVL_UJI_DIAG]]
 
Source: clkspeed.dol in [[RVL_UJI_DIAG]]

Latest revision as of 16:00, 6 May 2020

The Broadway is the Wii's main CPU. It is a 32-bit PowerPC CPU based on the PowerPC 750CL. It is based on the GameCube Gekko CPU design, being almost identical other than an overclock and the addition of a few new features.

New features from Gekko

(following text copied from official document "Summary of changes to Gekko User's Manual to turn it into a Broadway User's Manual")

The major changes from Gekko to Broadway, covered in the UM are:

  • 1) L2 cache configurable for 32-B fetch mode, 64B-fetch mode or 128B-fetch mode
  • 2) Deeper pipelining on the 60x bus, programmable to max depth of 2, 3 or 4
  • 3) Number of BATs is increased from 4 to 8 each for I and D
  • 4) Addition of the HID4 register (SPRN = 1011) to control the new features.
  • 5) TAU functionality is eliminated (but the THRM1-3 regs remain)
  • 6) PLL configuration (processor-to-bus frequency ratio) expanded
  • 7) Several changes to the signal pins - DRTRY, TLBISYNC, PLL_CFG[4]
  • 8) Several Gekko errata are fixed on Broadway.
  • 9) The PVR is initially 0x00087100 on Broadway.

Versions

  • DD1.0
  • DD1.01
  • DD1.2
  • DD1.3
  • DD2.0 (final)

Source: clkspeed.dol in RVL_UJI_DIAG